Prashant Kumar answered . 2024-05-18 03:39:46

  error_sample u_error_sample (.Trigger(error_sample_1),
                               .reset(reset),
                               .In1(Switch_out1),  // ufix6
                               .vsampled_latch(error_sample_out1)  // ufix6
                               );
                             


`timescale 1 ns / 1 ns

module error_sample
          (Trigger,
           reset,
           In1,
           vsampled_latch);


  input   Trigger;
  input   reset;
  input   [5:0] In1;  // ufix6
  output  [5:0] vsampled_latch;  // ufix6


  reg [5:0] In1_hold;  // ufix6


  always @(posedge Trigger or posedge reset)  // <=== input Trigger signal used as clock signal
    begin : vsampled_latch_hold_process
      if (reset == 1'b1) begin
        In1_hold <= 6'b000000;
      end
      else begin
        In1_hold <= In1;
      end
    end



  assign vsampled_latch = In1_hold;

endmodule  // error_sample

Please check the attached generated code for the model.

>> makehdl('Simulink_PI_Triggered/Discrete Compensator', 'TriggerAsClock', 'on')
### Applying HDL optimizations on the model 'Simulink_PI_Triggered'...
### Begin model generation.
### Model generation complete.
### Begin Verilog Code Generation for 'Simulink_PI_Triggered'.
### Working on Simulink_PI_Triggered/Discrete Compensator/error_sample  as hdlsrc\Simulink_PI_Triggered\error_sample.v.
### Working on Simulink_PI_Triggered/Discrete Compensator/prev_sample1 as hdlsrc\Simulink_PI_Triggered\prev_sample1.v.
### Working on Simulink_PI_Triggered/Discrete Compensator/prev_sample2 as hdlsrc\Simulink_PI_Triggered\prev_sample2.v.
### Working on Simulink_PI_Triggered/Discrete Compensator as hdlsrc\Simulink_PI_Triggered\Discrete_Compensator.v.
### Code Generation for 'Simulink_PI_Triggered' completed.
### Creating HDL Code Generation Check Report Discrete_Compensator_report.html
### HDL check for 'Simulink_PI_Triggered' complete with 0 errors, 1 warnings, and 0 messages.
### HDL code generation complete.

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